Intelligrated ……

Ben Thompson of Stratchery in his recent blog on Intel Split prompted me to coin the word “Intelligrated“, which is a counterpoint to his thesis. – No, its not in the dictionary. Before we get to that, lets start with one topic he brings up as it is near and dear to me and many of my old fellow chip nerds from that time (1987-2003) which I would call as EDA 1.0 era.

EDA changed microprocessor roadmap starting Circa 1987 and continued through late 1990s: Ben references Pat’s paper on Intel EDA methodology which scaled design methodology to track moore’s law. Intel invested heavily in EDA internally as the industry was immature. Around the same time Sun Microsystems which built its business selling EDA/MCAD workstations was changing the industry EDA landscape (methodology and eco-system). [An aside: Would not be surprised if x86 CPUs till Pentium IV, were designed using Sun workstations]. Both companies had parallel but different approaches.

EDA 1.0: Intel vs Sun approach: Sun’s approach was industry tools and if it does not exist enable the industry eco-system to be built. It perhaps started in 1989 when a motley crew (25) of engineers (including yours truly) built the first CMOS SPARC SOC (Tsunami – referenced here) with no prior experience in custom VLSI. We all came out of a cancelled ECL SPARC microprocessor where none of us had done any custom VLSI design. The CAD approach was…

Necessity is the mother of invention. Sunil Joshi captured the EDA methodology then in the MicroSPARC HotChips presentation. 486 (Pat’s chip) had 1.2M transistors (100+ engineers perhaps) vs the more integrated MicroSPARC at 800K transistors that came 2 years later (same time as Pentium which had 200+ engineers) but a full SOC. AS noted, we had only 2 mask designers and every engineer had to write RTL, synthesize, verify, do their own P&R, timing analyze and two of us built the CAD flow so that it can be push button. Auto-generated standard cells were automatically P&R using compiler tools. That was not the norm for ‘custom VLSI’ circa 1991 for that scale.

That eventally got the name ‘Construct by correction vs Correct by construction’ and throughout the 1990s, this evolved, scaled and made the processor design competitive as well raised a lot of boats in the EDA industry that evenutally got Intel to adopt industry tools with a healthy mix of in-house tools. With no in-house EDA teams, we creatively partnered (Synopsys, Mentor), invested (Magma, mid 1990s), helped M&A (gateway design – verilog, Cooper and Chyan – Cadence), spin-out (Pearl timing analyzer to replace motive). At the same time IBM EDA tools which were superior to both Sun’s approach and Intel, but was locked up inside IBM until later in the decade, when it was too late.

In parallel, there was a great degree of systems innovation (SoCs, glue-less SMP, VIS, Ethernet, graphics accelerators, multi-core+threading) that was enabled by EDA 1.0 and CMOS custom VLSI by the industry at large with Sun leading the parade. Allow me to term it as ISM 1.0 (Integrated Systems).

Now IDM 1.0 is what made Intel successful to beat all the RISC vendors. We (Sun and compatriot RISC vendors) could beat Intel in architecture, design methodology and even engineering talent and in some cases like Sun which had OS and Platform built a strong moat. But, we could not beat Intel on manufacturing technology. Here’s a historical view of tech roadmap.

Tech History (litho nm only)

Caution: Given dated history, some data from 1990s could be incorrect – corrections please notify.

In a prior blog I have called out how Intel caught up with TI and IBM on process technology by 1998 (they were the manufacturing leader but not the technology leader w.r.t xtor FOM or metal litho until 1998). TI Process technlogists used to complain ‘At Intel design follows fab and you folks are asking fab to follow design’ as we demanded xTOR FOM and Metal litho more than Moore in the 1990s. By 1998 with coppertone, Intel raced ahead with both litho as well as xtor FOM (60% improvement in 180nm with coppertone to boost Pentium MhZ). So Intel was not xtor FOM leader in early 1990s, but they pulled ahead by 1-2 generations by late 1990s. It has been done by Intel. When they did go ahead is when IBM and TI became non-competitive (starting 1998) for high end microprocessors and the beginning of our end and my departure from microprocessor (unless I go to Intel). (Side note: Both TI and Intel bet on BiCMOS till 650nm). Unlikely history will repeat itself as the dynamics are different today with consolidation, but it has been done before by Intel.

Intel’s leadership with IDM 1.0 and co-opting ISM 1.0 architectural elements (by 2002 – multi-core, glue-less SMP, MMX, integrated DRAM controllers) into its processors made it difficult for fabless CPU companies to thrive despite having systems business to fund – which was not sufficient by 2002. Even 500K CPUs/year (Sun/SPARC) was not economically justifiable. IBM, SGI, HP and many more esp. dropped as cost of silicon design and tech went up. [Side note: I am not sure on a standalone basis Graviton is economically viable for Amazon – if 500K CPUs was not viable in 2000, 50K is certainly not viable in 2020 – but sure they can wrap other elements in the TCO stack to justify for a few generations – not sustainable over 3-5 generations). Regardless, 20 years later…

IDM 2.0 is a necessary first step and good that Pat & Intel are putting that focus back. But IDM 2.0 needs ISM 2.0 and the same chutzpah of late 1980s of design EDA innovation but this time perhaps own the ‘silicon systems platform SW stack’.

ISM 2.0 is ‘Integrated Systems 2.0’. If SoC were the outcome of Moore’s law in the 1990s, SoP (Systems on Package) is the new substrate to re-imagine systems as the platform is becoming heterogenous for compute (CPU, DPU, IPU, xPU), Memory (DRAM, 3D xpoint, CXL memories) and Networks (Ethernet and CXL). There will always be a CPU (x86 or ARM), but increasingly we will find a DPU/IPU/XPU in the system that sweeps all the new workloads. The IPU/DPU/GPU/XPU will increasingly be an SoP with diversity of silicon types to meet the diversity of workload needs. But it will need a common and coherent software model to be effective in enabling platforms and workloads including low level VMs or run-time with standard APIs (e.g. P4/Sonic, Pytorch+TF and others).

On economies of scale which killed the RISC revolution (amongst other reasons), I have written about SoC vs SoP in a different blog here, but its important to consider the diversity of customers from OEM platforms to cloud platforms, emerging telco/edge service providers, and emerging ML/AI or domain specific service providers that have a large TAM. Each one needs customization i.e. no more one size fits all platforms, its multiple chips into multiple SoPs to different ways to package and deliver to these new channels of delivery – OEM (Single System), Cloud (distributed systems) and emerging decentralized cloud. But to retain the economies of scale of chip manufacturing while delivering customized solutions to the old and new category of customers, we are moving towards disaggregate at the component level and aggregation at the platform software level.

Just to get a better sense of varied sales motion- Nvidia is a chip company, a box company (mellanox switches and DGX) as well as a cloud company (delivering ML/AI as a service w/Equinix).

This is more than Multi-core and Virtualization that happened in Circa 2003 (VMware). An entire new layer of software will be a key enabler for imagining the new ‘integrated systems’ and delivery of them. For lack of a better TLA , let me call it EDA 2.0. The design tooling to assemble these variety of SoP solutions requires new design tooling to enable customization of the ‘socket’. The old mantra was sell 1 chip SKU in millions. That is still true. But we will have multiple SoP SKUs using the same multi-million unit chip SKU. The design tooling to assemble these SoP has not only manufacturing programmability but in the field as there will be some FPGA elements in the SoP as well as low level resource management functionality.

Hijacking the OSI model as a metaphor to represent the infrastructure stack…..

7 layers of Infrastructure Stack
Bottom 3 layers form the emerging silicon systems plane

The homogenous monolithic CPU has now become heterogenous CPU+DPU/IPU/XPU/FPGA. Memory from being homogenous DDR to DDR + 3Dxpoint on DDR bus and CXL bus.

So ‘Integrated Systems’ is an assembly of these Integrated chips based on target segments and customers, but have to manage the three axes of flexibility vs performance vs cost. While silicon retains that one mask set for most target segments (economics), the customization at the packaging level enables the new ‘integrated system’ (the bottom three layers in above visual) . This new building block will become complex over time (hardware and software) thus value extraction (simplification of complexity results in value extraction) but requires capital and talent. Both exists ironically either with the chip vendor or with the cloud service provider, the two ends of the current value chain.

The pendulum is starting swing back from the vertically integrated chip company (1980-2000) to the era when OEMs owned Silicon (Sun, HP, IBM) or chip companies owned fab (Intel), to Horizontalization with the success of fabless chip (Nvidia, Broadcom……) + TSMC (2000-2020) to again vertical integration at sub-system level for certain segments or markets.

Back to Intel Split vs Intel Integrated. In this era, if there is any lesson learnt from the EDA 1.0 era, it would be smarter to do a build, buy and partner i.e. build the new tooling (EDA 2.0 and BIOS 2.0) in a smart combination of build, buy, partner and expand into invest, open source and build a moat around that eco-system that will be hard for competitive chip companies to compete. EDA 2.0 is not the same as EDA 1.0 – its both design tools pre-manufacturing and low level programming and resource management frameworks. Directionally some of it is captured here by Chris Lattner ( MLIR & CIRCT). We have a chicken and egg situation that to create that layer we will need new silicon constructs, but to get to the right silicon, you will need the new layer (akin to how Unix+C enabled RISC and RISC accelerated Unix and C eventually referenced here..)

Coming back to Intel v TSMC and splitting, TSMC is good at manufacturing – but has not (yet) built eco-systems and platforms at higher levels. Its their customers (fabless). Intel knows that and done that many times over. I make the case that Intel Integrated with IDM 2.0 and ISM 2.0 and being flexible in delivery SoC, SoP and even rack level products to emerging decentralized-edge cloud providers will the emerging opportunity.

Splitting the company will devalue the sum of parts than being whole in this case. While, the point of split (fab) driving accountability and customer focus and serviceability is there, there are perhaps other ways to achieve the same without a formal split while retain the value of integration of the parts.

Smart integration of the various assets and delivery. Creatively combining design engineering, EDA 2.0, BIOS 2.0 and linking it to SoP and SOC manufacturing including field level customization will be a huge value extraction play. The Apple vs Android model of market share vs margin share. IDM 2.0 with ISM 2.0 will get market share and margin share for dominant compute platforms.

A POV – Intel has do 3 things. IDM 2.0 (under way), ISM 2.0 (will elaborate that in a future note) and something else ( aligned with Intel’s manufacturing DNA) truly out of the box before 2030 when its going to be economically and physically hard to get more from semiconductors as we know. That has to be put in place between now and 2030…

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References to EDA at Sun…

Historical CPU/Process Node Data..

SoC to SoP

A reflection of moore’s law, personal history and coming Tsunami of Systems

This blog was prompted by Pat Gelsinger in his recent keynote talking about Systems on Package (SOP). That brought memories of Systems on a Chip (SoC) – back to Circa 1991. While this term is common in the lingua franca of chip nerds these days, it was not the case back in 1991. Perhaps one of the first SoCs on the planet was one in which I was lucky to be involved with that also helped bootstrap my professional life in Silicon and Systems. It was Microsparc-I (aka Tsunami) while at Sun and that had a few firsts. All CMOS, first SoC and had a TAB package. All-in-one.

Image result from https://www.computerhistory.org/collections/catalog/102626774
MicroSPARC – 1 in a TAB package (Circa 1991)

This chip was in the system. Good to know its in the computer history museum archives.

Image
SparcStation

The label Sun 386i was a joke. Used to have Sun 386i platform and the joke was, this was faster and cheaper than any PC then.

Image
SparcStation
Image
MicroSPARC-1 on the board

That was the beginning of my semiconductor run in my professional life. It started with an ECL machine for SPARC we did back in 1987-1990, which got shelved eventually as it was going to be hard to manufacture and sustain volume production. Some of us without a job, were asked to work on a ‘low cost’ SPARC and work with TI on their 0.8uM CMOS process. While the rage then was BiCMOS (SuperSPARC for Sun) and Intel Pentium. It showed Intel despite being a tech and manufacturing power house, has made mistakes in the past, not just recently…We will come to that

The First SoC (Microprocessor SoC) had many firsts back in 1991.

  1. It was all CMOS (when BiCMOS and ECL were still ruling the roost
  2. It was all integrated (Integer Unit, Floating Point Unit, Icache, Dcache, MMU/TLBs, DRAM controller (SDRAM) and Sbus Controller (Pre PCI).
  3. It was in 0.8 uM CMOS (TI) and in a TAB package (as seen above)
  4. It was entirely Software driven tool chain – the physical layout was done with Mentor GDT tools – programmatically assemble the entire chip form basic standard cells and GDT P&R tools, Synopsys synthesis, Verilog. All SW driven Silicon – A first. There is a reference to it here. This led to the entire EDA industry rallying around the way Sun designed microprocessors and a whole sleuth of companies formed around that (Synopsys, Ambit, Pearl, CCT->Cadence and many many more).
  5. It was the beginning of the low cost workstation (and server) – approach $1000 and ‘fastest’ from a clock rage (MHz – when that was the primary performance driver in the early years).
  6. From 1991 through 2003 by the time I left Sun, was involved in 8 different generations/versions of SPARC chips and looking back, the Sun platform/Canvas not only helped me be part of the team that changed the microprocessor landscape, we changed the EDA industry and by late 1990s brought ODM manufacturing to traditional vertically integrated companies to completely outsource systems manufacturing.

A visual of the height of Moore’s law growth and the success I rode with that Tsunami (Co-incidently the first chip for me was named Tsunami). From 0.8 uM 2LM CMOS to 0.65uM 10 LM CMOS. From 50 MHz to 2 GHz, 0.8M xtors to 500M xtors.

1991-1994 – Microsparc – The first CMOS SoC Microprocessor that extended Sun workstations and servers to the ‘low end’ and drove technology leadership with EDA companies named above in driving many ‘SW driven VLSI’. We built the chip with the following philosophy ‘construct by correction’ vs ‘correct by construction’ – which was the prevailing methodology. In modern parlance of Cloud – its DevOps vs ITops.

1995-1998 – UltraSPARC II and IIe – With the introduction of 64 bit computing, we continued to lead both on architectural performance (IPC), semiconductor technology (lead CMOS @ TI along with IBM until Intel took control of that by 1998), Clock Rate and many system level innovation (at Scale Symmetric Multi-processor, glue-less SMP at low cost, Media instructions). This was the Ultra family of compute infrastructure that was the backbone of the internet until the dot-com bust (2001-2003)!

1998-2001 – UltraSPARC I & E series: Created 2 product families and both drove new business ($1B+) for Sun. The Telco/Compact PCI business went form $0 to $1B in no time, the extension of workstations and servers to $1K and glue-less SMP (4-way) for <$20K, another industry first. The beginning of NUMA issues and pre-cursor to the dawn of the multi-core era. UltraSPARC IIi (codenamed Jalapeno) was the highest lifetime volume CPU for the entire lifetime of SPARC.

Clock Rate (SPARC vs x86)

While clock rate is not a good representation of actual device technology improvements, its the best first order relative metric I can share here given the dated history. Suffice it to say as you can see, until 1998 we had good technology (CMOS) FOM improvements per node until 0.18uM (Intel coppertone), when Intel decided to boost its performance by 60% when the industry average was 30%. That was the beginning of the end on two fronts – Sun + TI having enough capital and skills to keep up with the tech treadmill against Intel (althought we introduced copper for metal ahead of Intel) and the decision to start shifting architecture from pure IPC and clock to multi-core threading. Recognizing this, I started the multi-core effort around Circa 1998, but it took another 5 years to bear fruit. I digress.

As a side note: Look at Intel technology improvement performance lately. I would never have in my wildest imaginations thought this would happen.

2001-2003 – Dawn of Multi-core and threading: While the results of these happened in 2001-2003, the seeds of this were sown in both multi-core in the form of dual core UltraSPARC IIe and eventually Niagara (UltraSPARC T Series).

The next 10 Year years is going to be as dramatic as the 1990s for completely different reasons at the system level. While Moore’s law has slowed down, the SoP is an important and critical technology shift to enable one to keep up the effective Moore curve. With Moore you got performance, power and cost at the same time./ We won’t get all three, but we can strive 2 out of 3 – i.e. Performance at constant cost or power.

SoP (Systems on Package) is an important milestone and glad to see Intel leading that and so is AMD and rest – but this can be a compelling way to construct the new system. In the next blog we will explore why the next 10 years is going be disruptive at the system level, but SoP like SoC and CMOS+Moore law was the Tsunami wave that raised a lot of boats including my career, many companies success and changed the industry and computing stack in a fundamental way.

I expect many firsts or changes or disruptions from design methodology to now customization by customer of various heterogenous silicon components (CPU, IPU, FPGA, memory elements and a lot more). Associated with that will be tools to assemble this, but also tools to make these look like one monolithic’ fungible computing element to the end user.

Virtualization to-date has been dominated by leveraging multi-core and improving utilization by spawning of many VMs that subdivide the machine into smaller chunks. New software layers either above or below the standard frameworks like Lambda (Server-less), PyTorch/TF (ML/AI) or Crypto will drive new ways to effectively use the dramatic increase in total silicon real estate including tiering of memory, scheduling code chunks to accelerators in coherent space (via CXL), new intra-rack and intra-node connectivity models via CXL and many more to come. Strap in for that ride/discussion. HW is getting more disaggregated from aggregation that started back in 1991 via SoC to now with SoP , Software will have to do the ‘aggregation’.

As I signoff, will share some more images from the 25 year anniversary of SPARC is captured here in this montage below.

$TSLA – Marching towards $10T by 2030……

First Trillionaire and 10 Trillion dollar company.

This is my 4th post on the topic of $TSLA and never thought I would do one in 2021. My predictions was a valuation of $1T by 2030. That will come and pass rather soon.

My first post on $TSLA was back in June, 2017 where the core value long term I thought was Chemistry (Battery) and Intelligence (Full Self Driving/Autonomy). That continues to be the case with Elon’s battery day (Sep’20) & Tesla Autonomy day on April 2019.

So why $10T? That seems to be even more ridiculous than the $1T. Since Feb’20 to now it has gone by 4x and $600B market cap. While there are lots of bears, there are lots of bulls as well for the TSLA case.

Bull Case #1: The bull case is presented by Ark Invest (Source: Ark Invest). Having crossed 500K in 2020 and total of 1M+ with 2 additional factories (Austin and Berlin) yet to come online, getting to 1-2M by 2025 is highly likely and approaching 5M might be difficult, but then Elon has beaten the odds and the market is expecting him to with the demand.

2020Example Bear Case 2025
Cars Sold (millions)0.55Example Bull Case

10
Average Selling Price (ASP)$50,000$45,000$36,000
Electric Vehicle Revenue (billions)$26$234$367
Insurance Revenue (billions)Not Disclosed$23$6
Human-Driven Ride-Hail Revenue (net, billions)$0$42$0
Autonomous Ride-Hail Revenue (net, billions)$0$0$327
Electric Vehicle Gross Margin (ex-credits)21%40%25%
Total Gross Margin21%43%50%
Total EBITDA Margin*14%31%30%
Enterprise Value/EBITDA1621418
Market Cap (billions)673$1,500$4,000
Share Price**$700$1,500$4,000
Free Cash Flow Yield0.4%5%4.2%
Ark Invest Projections

What’s interesting is TSLA has single-handely taken out the $35K- $100K market which the Germans dominate and Toyota tried hard to penetrate with incremental engineering and marketing. TSLA changed the game and will perhaps go as low as $25K but not lower is my guess. TSLA will license IP (Chemistry and Intelligence) and let others make the cars. The entire $35K to $100K is now ‘owned’ by TSLA and its going to be harder for most makers other than the BMW or Mercedes and they will be supported by ardent fans latched onto the brands. 2018 data for segmentation of the various categories is shown here.

2018-worldwide-car-sales-segments

Source: https://carsalesbase.com/global-car-sales-2018/

As you can see from above, 62.8% of the market will be covered by Tesla with Model 3, Model Y, Model S, Cybertruck and perhaps upcoming new China sourced $25K model. That includes the SUV, Midsize, MPV, Pickup, Executive, Sport and Luxury segments. The total market size is 54M cars and if Tesla can get 20% of that category – which actually is possible (we are in winner take all world these days with Amazon, Google, Apple where its tech driven) relative to conventional wisdom of highly fragmented and splintered market for automobiles.

Bull Case #2: Its what I mentioned in the last year. One has to look at TSLA as a business of businesses. Expect in the next 5 years, either take the Alphabet (GOOG) route or via other routes (Spin-offs, M&As, SPACs ….) derivative businesses will emerge and stand on their own. To re-cap

  1. A car company
  2. A Battery company at planet scale
  3. An AI/ML company (machine vision in particular)
  4. An electric storage company
  5. An Electric Utility company (low value but at scale gets interesting)
  6. An energy distribution company
  7. A potential Cloud or computer company (if a book store turns into cloud computing, an autonomous car can have the right assets for becoming a cloud company)
  8. A big data/mapping/navigation company
  9. A carless car company (i.e. Uber/Lyft killer robotaxi)
  10. A machine vision driven robotics company
  11. and more to come….(more than letters in the Alphabet)

Elon himself quoted a version of this back in Oct’2020

Bull Case #3: Chemistry and Intelligence. Every tech category goes through vertical integration and horizontal stratification. I speculate Elon will build down to a $25K car and below that, he will ‘license’ IP (Chemistry and Intelligence or battery tech and autonomy tech) to get worldwide reach. It would not make sense to have factories all over the world for all geos – but a strong IP revenue model ($1-$2K/car) could be had and also enable new players in countries to become car companies – i.e. more local manufacturing and distribution. And not just limited to cars, for all kinds of transportation and perhaps energy sectors. From the chart above the remaining 35% of the segments (Compact, Sub-Compact, City-car) would belong in this category. Of the 86M cars sold in 2018 (I suspect its less in 2021), 30M cars would be in this category. If 20% of the manufacturers pay TSLA $1K-$2K – lets assume $1K – that is $6B of pure profits which is subsidized by the higher end. The TSLA brand will be more valuable and trusted over VW, Mercedes, BMW, Toyota by 2025 that most people would buy a car ‘Tesla powered’. At this rate of battery cost decline (see blow), these manufacturers who cannot afford R&D or manufacturing at scale would do well to buy it off TSLA. This is akin to INTC holding onto x86 and not having an IP model which let ARM into its turf. Imagine if INTC had both a vertically integrated model of CPUs and a licensing model for some components – AAPL would be in Intel’s camp and so would the big three hyperscalers. Pat Gelsinger is trying to get Intel back into that game in 2021 (which we will address in a different blog post). But if TSLA were to choose both models, a vertically integrated model for some categories and an IP or sub-component sale to other categories, they can cover the entire spectrum and make the brand even more ubiquitous and higher moat.

TSLA is handicapped relative to VW and Toyota on manufacturing scale and distribution reach. The aggressive ramp of manufacturing of the car and IP model will broaden the reach and create other businesses (Robo Taxi, Energy Storage/distribution, Cloud computing for AI and many more to come).

Bill Gates famouly said ” We overestimate what we can do in 2 years and underestimate what humanity will achieve in 10″. One has to do a version for Elon. He over-promises what’s coming in 2-3 years, but delivers on a 10 year vision. If you look back what he has said in 2011/2012 – and see what has been accomplished – its not that far off.

We will revisit this blog in 2025 if we have crossed the Ark Invest marker and if TSLA is barrelling past $3-$4T and march towards the first $10T company on the planet (or maybe a collection of companies).

wrong tool

You are finite. Zathras is finite. This is wrong tool.

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"knowledge speaks but wisdom listens" Jimi Hendrix.

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